Vertical integration, that is, the stacking of multiple dies, has been proposed as a way to increase the density of integrated circuits. Constraints in vertical integration include the minimum thickness of each stacked component and the minimum thickness of the substrate of each component. An IC wafer may be thinned to an extent by grinding back the substrate of the IC. However, grinding can introduce unwanted stresses and dislocations on the wafer that can negatively impact IC performance and yield. An IC device wafer may typically be about 750 microns thick. However, the device layer may only be about 2-3 microns thick. A significant amount of the IC wafer, typically silicon, may therefore be unused or wasted material.